15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / Hochberger, Christian ; Nelson, Brent ; Koch, Andreas ; Woods, Roger ; Diniz, Pedro  

Público ISBD Ningún comentario para este registro. Título : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings Tipo de documento: documento electrónico Autores: Hochberger, Christian, ; Nelson, Brent, ; Koch, Andreas, ; Woods, Roger, ; Diniz, Pedro, Mención de edición: 1 ed. Editorial: [s.l.] : Springer Fecha de publicación: 2019 Número de páginas: XIII, 418 p. 217 ilustraciones, 110 ilustraciones en color. ISBN/ISSN/DL: 978-3-030-17227-5 Nota general: Libro disponible en la plataforma SpringerLink. Descarga y lectura en formatos PDF, HTML y ePub. Descarga completa o por capítulos. Palabras clave: Ordenadores  Sistemas operativos (computadoras)  Ingeniería de software  Sistemas informáticos  Computadoras  Propósitos especiales  Inteligencia artificial  Hardware de la computadora  Sistemas operativos  Implementación de sistema informático  Sistemas de propósito especial y basados ​​en aplicaciones Índice Dewey: 4 Resumen: Este libro constituye las actas del 15º Simposio Internacional sobre Computación Reconfigurable Aplicada, ARC 2019, celebrado en Darmstadt, Alemania, en abril de 2019. Los 20 artículos completos y 7 artículos breves presentados en este volumen fueron cuidadosamente revisados ​​y seleccionados entre 52 presentaciones. Además, el volumen contiene 1 artículo invitado. Los artículos se organizaron en secciones temáticas denominadas: Aplicaciones; reconfiguración parcial y seguridad; procesamiento de imágenes/vídeo; síntesis de alto nivel; CGRA y procesamiento de vectores; arquitecturas; marcos de diseño y metodología; Redes neuronales convolucionales. Nota de contenido: Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design / A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. En línea: https://link-springer-com.biblioproxy.umanizales.edu.co/referencework/10.1007/97 [...] Link: https://biblioteca.umanizales.edu.co/ils/opac_css/index.php?lvl=notice_display&i 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings [documento electrónico] / Hochberger, Christian, ; Nelson, Brent, ; Koch, Andreas, ; Woods, Roger, ; Diniz, Pedro,  . -  1 ed.  . - [s.l.] : Springer, 2019 . - XIII, 418 p. 217 ilustraciones, 110 ilustraciones en color. ISBN : 978-3-030-17227-5 Libro disponible en la plataforma SpringerLink. Descarga y lectura en formatos PDF, HTML y ePub. Descarga completa o por capítulos. Palabras clave: Ordenadores  Sistemas operativos (computadoras)  Ingeniería de software  Sistemas informáticos  Computadoras  Propósitos especiales  Inteligencia artificial  Hardware de la computadora  Sistemas operativos  Implementación de sistema informático  Sistemas de propósito especial y basados ​​en aplicaciones Índice Dewey: 4 Resumen: Este libro constituye las actas del 15º Simposio Internacional sobre Computación Reconfigurable Aplicada, ARC 2019, celebrado en Darmstadt, Alemania, en abril de 2019. Los 20 artículos completos y 7 artículos breves presentados en este volumen fueron cuidadosamente revisados ​​y seleccionados entre 52 presentaciones. Además, el volumen contiene 1 artículo invitado. Los artículos se organizaron en secciones temáticas denominadas: Aplicaciones; reconfiguración parcial y seguridad; procesamiento de imágenes/vídeo; síntesis de alto nivel; CGRA y procesamiento de vectores; arquitecturas; marcos de diseño y metodología; Redes neuronales convolucionales. Nota de contenido: Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design / A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. En línea: https://link-springer-com.biblioproxy.umanizales.edu.co/referencework/10.1007/97 [...] Link: https://biblioteca.umanizales.edu.co/ils/opac_css/index.php?lvl=notice_display&i

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